Semiconductor device fabrication operations are commonly used to manufacture components onto a semiconductor substrate to form a semiconductor wafer. The semiconductor device fabrication operations use predetermined sequences of photolithographic and/or chemical processing steps to form components onto the semiconductor substrate. However, imperfections of the semiconductor substrate, imperfections of the semiconductor device fabrication operation, and/or imperfections in design of the components themselves due to process variations in the sequences of photolithographic and/or chemical processing steps, may cause one or more of the semiconductor components to be formed differently than expected.
Conventional automatic test equipment (ATE) is commonly used to verify that the semiconductor components within the semiconductor wafer are formed and operate as expected. The conventional automatic test equipment includes a full complement of electronic testing probes to carry out a testing operation. This full complement of electronic testing probes includes electronic testing probes to apply power, digital testing signals, and/or analog testing signals to each of the semiconductor components to perform the testing operation. This full complement of electronic testing probes also includes electronic probes to read signals at various nodes of the semiconductor components to verify that each of the semiconductor components operates as expected during the testing operation. However, some microprocessor defects and variations do not cause testable electrical failures, although these defects may cause anomalies that lead to electrical failures or unexpected performance degradation in the chip's field operation.
Chip imaging may provide an additional level of information about these defects and anomalies. Chip imaging typically includes using various imaging techniques to take a picture of the electrical activity on the chip. For example, the imaging techniques may include detecting heat signatures (e.g., thermal imaging), photon signatures (e.g., photon imaging), and/or magnetic signatures (e.g., magnetic imaging) of actual electrical activity on the chip. However, the use of chip imaging to achieve the additional level of information about these defects and anomalies produces high variability images where discerning the defects or anomalies from normal behavior or variation is nearly impossible.
Therefore, the current methods for identification of potential future fails of chips remains limited to statistical screening based on chip parametric data and traditional burn-in testing without the use of chip imaging. Accordingly, there exists a need in the art to overcome the deficiencies and limitations described hereinabove.